1. Field of the Invention
The present invention relates to a semiconductor device incorporating a tester circuit to test a semiconductor device, particularly a semiconductor memory device. The present invention also relates to the structure of a testing device to test a semiconductor device incorporating such a tester circuit.
2. Description of the Background Art
Most semiconductor memory devices include spare memory cells to allow a defective memory cell, if present, to be replaced with the spare memory cell to repair the defective chip.
FIG. 19 is a schematic block diagram showing a structure of a redundant circuit provided for a memory array unit 8010 of such a semiconductor memory device.
One memory cell in memory array unit 8010 is selected by externally applied row address signals RA0-13 and column address signals CA0-8. In a write operation, the data applied to a data input/output terminal DQ (not shown) is written into the selected memory cell. In a read out operation, the data read out from memory array unit 8010 is provided to data input/output terminal DQ.
A row decoder 8020 responds to the input row address to select memory cells of one row for a read or write operation. A column decoder 8030 selects one column according to the input column address and further selects one memory cell out of the one row of memory cells selected according to the row address.
In the structure of FIG. 19, two spare rows SR1 and SR2, and two spare columns SC1 and SC2 are provided as the spare memory cells. Spare row SR1 is constituted by one row of memory cells SRM1 and a spare row decoder SRD1. Spare row SR2 is constituted by one row of memory cells SRM2 and a spare row decoder SRD2.
Spare column SC1 is constituted by one column of memory cells SCM1 and a spare column decoder SCD1. Spare column SC2 is constituted by one column of memory cells SCM2 and a spare column decoder SCD2.
In spare row decoders SRD1 and SRD2, a row address corresponding to a defective memory cell is recorded in advance. The input row address is compared with the row address corresponding to the defective memory cell. When the row addresses match, a corresponding spare memory cell SRM1 or SRM2 is selected. When spare row memory cell SRM1 or SRM2 is selected, spare row decoders SRD1 and SRD2 control row decoder 8020 so that a memory cell of the normal memory array is not selected.
Similarly, a column address corresponding to a defective memory cell is recorded in advance in spare column decoders SCD1 and SCD2. Spare column decoders SCD1 and SCD2 compare the input column address with this recorded column address corresponding to a defective memory cell. When the column addresses match, a corresponding spare column memory cell SCM1 or SCM2 is selected. When spare column memory cell SCM1 or SCM2 is selected, spare column decoders SCD1 and SCD2 control column decoder 8030 so that a memory cell in the normal memory array is not selected.
In the case where there is a defective memory cell in the memory array, that memory cell is replaced by spare rows SR1 and SR2 or spare columns SC1 and SC2 to repair the defective memory cell. For example, consider the case where there are defective memory cells DBM1 to DBM8 in the memory array, as shown in FIG. 19.
It is assumed that defective memory cells DBM2-DBM4 correspond to the same row address RF2, and defective memory cells DBM3 and DBM5-DBM7 correspond to the same column address CF3.
Therefore, by replacing the rows corresponding to row addresses RF1 and RF2 in the normal memory array with spare rows SR1 and SR2, and by replacing the columns corresponding to column addresses CF3 and CF8 with spare columns SC1 and SC2, memory array 8010 can be repaired.
FIG. 20 is a schematic block diagram showing a structure of a memory tester 9000.
Memory tester 9000 has a redundancy analysis function to detect a defective memory cell in a semiconductor memory device 8000 and to determine whether semiconductor memory device 8000 can be repaired by replacement with either a spare row or a spare column.
Memory tester 9000 includes a signal generator 9010, a comparator 9020, a failure memory 9030, and an analysis device 9040.
Signal generator 9010 generates and provides to semiconductor memory device 8000 that is the subject of measurement row address signals RA0-13, column address signals CA0-8 and write data TD used for testing.
Although not shown, signal generator 9010 also generates other control signals such as a write enable signal WE, a chip select signal /CS, a row address strobe signal /RAS and a column address strobe signal /CAS. which are provided to under-measurement semiconductor memory device 8000.
Furthermore, signal generator 9010 generates expected value data ED corresponding to write data TD in the read out operation in the test mode. Comparator 9020 compares the data output from semiconductor memory device 8000 with expected value data ED to determine whether under-measurement semiconductor memory device 8000 outputs the proper data. The determination result is output as a pass/fail signal P/F.
Failure memory 9030 includes storage elements identical in number with that of the memory cells in under-measurement semiconductor memory device 8000.
Failure memory 9030 stores the level of the determination resultant signal P/F output from comparator 9020 in the storage element specified by row address signals RA0-13 and column address signals CA0-8 output from signal generator 9010.
Analysis device 9040 reads out the data from failure memory 9030 to analyze which of the spare row and the spare column the defective memory should be replaced for repair.
Analysis device 9040 provides the address of the defective memory to be repaired to a repair device, for example, a laser trimmer device. The laser trimmer device programs the value of the defective address by trimming the fuse element provided in semiconductor memory device 8000. Details of laser trimming is disclosed in, for example, Japanese Patent Laying-Open No. 4-330710.
In a conventional memory tester 9000, the capacity of failure memory 9030 had to be increased reflecting increase in the memory capacity of under-measurement semiconductor memory device 8000. Failure memory 9030 is expensive and must allow high speed operation. Therefore, there was a problem that increasing the capacity of failure memory 9030 is costly.
Recently, a semiconductor memory device with a built-in testing device or a semiconductor device incorporating a semiconductor memory device with a built-in testing device are fabricated. The semiconductor device includes a signal generator 9010 to carry out testing without a memory tester. Although detection can be made whether there is a defective memory cell in the memory array in such semiconductor memory devices or semiconductor devices with the built-in testing device, it was difficult to effect a test realizing the redundancy analysis function itself. Redundancy analysis could not be carried out since it is difficult to incorporate in a semiconductor memory device or a semiconductor device a failure memory 9030 that requires a large amount of capacity equal to that of the under-measurement semiconductor memory device or the semiconductor memory device incorporated in a semiconductor device.